1 1 1 1 1 0 1 Tabel 2. Espresso tulemus Espresso tulemuse välja kirjutatuna saame: y1' = x2'x3' or x1' y2' = x2' y3' = x1'x2' or x3 y4 = x3 Eemaldades inversioonid saame: y1 = (x2'x3' or x1')' = (x2'x3')'x1 = x1(x2 or x3) y2 = x2 y3 = (x1'x2' or x3)' = (x1'x2')'x3' = x3'(x1 or x2) y4 = x3 Tallinn 2017 VHDL-i olulised kommenteeritud lõigud Testbench -- System of Boolean functions U1: f_system port map (x1, x2, x3, y1a, y2a, y3a, y4a);--mapib U1 tulemused -y1a,y2a,y3a,y4a peale U2: f_system port map (x1, x2, x3, y1b, y2b, y3b, y4b); U3: f_system port map (x1, x2, x3, y1c, y2c, y3c, y4c); U4: f_system port map (x1, x2, x3, y1d, y2d, y3d, y4d); y1x <= compare_signals (y1a, y1b, y1c, y1d); --võrdleb kõiki y1 tulemusi y2x <= compare_signals (y2a, y2b, y2c, y2d); --võrdleb kõiki y2 tulemusi y3x <= compare_signals (y3a, y3b, y3c, y3d); -- võrdleb kõiki y3 tulemusi y4x <=
x4)) ); end architecture espresso; Testpink ------------------------------------------------------------------------ -- IAY0150 - Homework #1. Test bench ------------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; entity test is end entity test; library IEEE; use IEEE.std_logic_1164.all; architecture bench of test is signal x1, x2, x3, x4: std_logic; signal y1a, y1b, y1c, y2a, y2b, y2c: std_logic; signal y3a, y3b, y3c, y4a, y4b, y4c: std_logic; signal y1x, y2x, y3x, y4x: std_logic; component f_system port ( x1, x2, x3, x4: in std_logic; y1, y2, y3, y4: out std_logic ); end component; for U1: f_system use entity work.f_system(tabel); for U2: f_system use entity work.f_system(espresso); for U3: f_system use entity work.f_system(opti); function compare_signals (s1, s2, s3: std_logic) return std_logic is begin if s1='-' then if s2/=s3 then return 'X'; end if;
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