"t4c" - 1 õppematerjal

IAY0150 - Digitaalsüsteemid I kodutöö

gates, kernels, no optimization. ------------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; entity f_system is port ( x1, x2, x3, x4: in std_logic; y1, y2, y3, y4: out std_logic ); end entity f_system; library IEEE; use IEEE.std_logic_1164.all; architecture opti of f_system is signal x1i, x2i, x3i, x4i: std_logic; signal t1a, t1b, t1c, t1d, t2a, t2b, t2c: std_logic; signal t3a, t3b, t3c, t4a, t4b, t4c: std_logic; begin x1i <= not x1; x2i <= not x2; x3i <= not x3; x4i <= not x4; t1a <= x3i or x4i; t1b <= x2 and t1a; t1c <= x2i and x3 and x4; t1d <= x1i and x4i; t2a <= x2i or x4i; t2b <= x1i and t2a; t2c <= x3i and x4i ; t3a <= x1 or x2; t3b <= x3i and t3a; t3c <= x1i and x3; t4a <= x1 and x3i; t4b <= x2 and x4i; y1 <= not(t1b or t1c or t1d);