Book Analog Interfacing to Embedded Microprocessors
Digital-to-Analog Converters 21
Figure 2.4
Dual-slope ADC.
since the same clock is used for charging and incrementing the counter. Note
that clock jitter or drift within a single conversion will affect accuracy.
The dual-slope converter takes a relatively long time to perform a conver-
sion, but the inherent filtering action of the integrator eliminates noise.
Sigma-Delta
Before describing the sigma-delta converter, we need to look at how oversam-
pling works, since it is key to understanding the sigma-delta architecture.
Figure 2.5 shows a noisy 3v signal, with .2v peak-to-peak of noise. As shown in
the figure, we can sample this signal at regular intervals. Four samples are
shown in the figure; by averaging these we can filter out the noise:
(3.05v + 3.1V + 2.9 V + 2.95 V ) 4 = 3 V
Obviously this example is a little contrived, but it illustrates the point. If our
annaabi.ee 
