Digitaalloogika ja digitaalsüsteemid
signal x1, x2, x3, x4 : bit;
signal y4, y7, y8, y9, y10 : bit;
component funktsioonid is
port (
x1, x2, x3, x4 : in bit;
y4, y7, y8, y9, y10 : out bit;
);
end component;
constant x1_vector : bit_vector(0 to 12) := "0000001111111";
constant x2_vector : bit_vector(0 to 12) := "0000110001111";
constant x3_vector : bit_vector(0 to 12) := "0011010110011";
constant x4_vector : bit_vector(0 to 12) := "0101010010101";
begin
process
begin
for i in x1_vector' range loop
x1 <= x1_vector(i);
x2 <= x2_vector(i);
x3 <= x3_vector(i);
x4 <= x4_vector(i);
wait for 10 ns;
end loop;
wait;
end process;
UUT: funktsioonid
port map (
x1 => x1,
x2 => x2,
annaabi.ee 
