Digitaalloogika ja Digitaalsüsteemid
11. Modelleerida punktides 4, 7, 8, 9, 10 saadud
tulemusi VHDL-is.
11.1 Testpink
Testpink on kõikidel simulatsioonidel sama.
entity testbench is
end testbench;
architecture bench of testbench is
signal x1, x2, x3, x4, y : bit := '0';
component funktsioon
port ( x1, x2, x3, x4 : in bit;
y : out bit
);
end component;
constant x1_arr : bit_vector(0 to 15) := "0000000011111111";
constant x2_arr : bit_vector(0 to 15) := "0000111100001111";
constant x3_arr : bit_vector(0 to 15) := "0011001100110011";
constant x4_arr : bit_vector(0 to 15) := "0101010101010101";
begin
process
begin
for i in x1_arr'range loop
x1 <= x1_arr(i);
x2 <= x2_arr(i);
x3 <= x3_arr(i);
x4 <= x4_arr(i);
wait for 5 ns;
end loop;
wait;
end process;
annaabi.ee 
