IAY0150 - Digitaalsüsteemid praktikumi ülesanne
port(a, b : in std_logic;
o : out std_logic);
end component;
signal x3i, x2x3or, x1x2or: std_logic; begin
U0: nand2 port map (x3, x3, x3i);
U1: or2 port map (x2,x3,x2x3or);
U2: and2 port map (x1,x2x3or,y1);
U3: y2 <= x2;
U4: or2 port map (x1, x2, x1x2or);
U5: and2 port map (x3i, x1x2or, y3);
U6: y4 <= x3; end
struct;
Tallinn 2017
Lisa 5. Testpink - testbench.vhd
library IEEE; use IEEE.std_logic_1164.all;
entity kaubamajaTest is
end entity kaubamajaTest;
library IEEE; use IEEE.std_logic_1164.all;
architecture bench of kaubamajaTest is signal x1, x2,
x3: std_logic;
signal y1a, y1b, y1c, y1d, y2a, y2b, y2c, y2d, y3a, y3b, y3c, y3d, y4a, y4b, y4c, y4d :
std_logic;
signal y1x, y2x, y3x, y4x: std_logic;
component f_system
port ( x1, x2, x3: in std_logic;
y1, y2, y3, y4: out std_logic );
end component;
for U1: f_system use entity work.f_system(tabel); for U2:
f_system use entity work
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